Motor drive converter and method with neutral point drift compensation

ABSTRACT

A high power motor drive converter comprises: a three level neutral point clamped (NPC) output power conversion stage including switches for supplying power to an AC drive motor; a split series connected DC capacitor bank coupled in parallel with the NPC output power conversion stage; and a controller for selecting switch positions for controlling the NPC output power conversion stage and compensating for a neutral point voltage imbalance of the DC capacitor bank by adjusting amplitudes of carrier voltages according to an amount of voltage imbalance in the split series connected DC capacitor bank.

BACKGROUND

[0001] The invention relates generally to motor drive converters and more particularly to three-level neutral-point-clamped converters.

[0002] Conventional converters include electrical switches paired with diodes to accommodate inductive motor load currents. Three phase three level inverters have three phase legs with each leg having four switch and diode pairs spanning a DC bus and two clamping diodes. A controller is used for controlling each of the switches, and there are three command states for the switches per phase. By coupling clamping diodes between the DC capacitor bank midpoint (the neutral point) and pairs of the switches, the maximum DC working voltage across any switch is kept from exceeding about one half of the DC bus voltage.

[0003] Conventional techniques for providing voltage balance for the neutral point include, for example, sine triangle modulation by inserting zero-sequence voltage and space vector modulation by manipulating small vectors. Examples of these techniques are described in Steinke, “Switching Frequency Optimal PWM Control of a Three-Level Inverter,” IEEE TRANSACTIONS ON POWER ELECTRONICS, Vol. 7, No. 3, 487-96, July 1992, and commonly assigned Lyons et al., U.S. Pat. No. 5,910,892. In such embodiments, the voltage balance in the neutral point can be achieved in a line cycle level. However, for certain loading conditions, significant charge flows in and out of the neutral point and can cause neutral point voltage ripple on multiples of the line frequency.

[0004] The conventional method for minimizing neutral point voltage ripple by increasing the DC link capacitance is expensive. It would therefore be desirable to minimize neutral point voltage ripple by a method that does not require increased DC link capacitance.

SUMMARY

[0005] Briefly, in accordance with one neutral point drift compensation embodiment of the present invention, a high power motor drive converter comprises: a three level neutral point clamped (NPC) output power conversion stage including switches for supplying power to an AC drive motor; a split series connected DC capacitor bank coupled in parallel with the NPC output power conversion stage; and a controller for selecting switch positions for controlling the NPC output power conversion stage and compensating for a neutral point voltage imbalance of the DC capacitor bank by adjusting amplitudes of carrier voltages according to an amount of voltage imbalance in the split series connected DC capacitor bank.

DRAWINGS

[0006] The features of the invention believed to be novel are set forth with particularity in the appended claims. The invention itself, however, both as to organization and method of operation, together with further objects and advantages thereof, may best be understood by reference to the following description taken in conjunction with the accompanying drawings, where like numerals represent like components, in which:

[0007]FIG. 1 is a circuit diagram of a conventional three-phase neutral-point-clamped converter.

[0008] FIGS. 2-3 are graphs illustrating implementation of a sine triangle three level modulation.

[0009] FIGS. 4-5 are graphs illustrating an implementation of a sine triangle three level modulation in accordance with one embodiment of the present invention.

[0010] FIGS. 6-7 are space vector diagrams illustrating effects of voltage unbalance in the neutral point.

[0011] FIGS. 8-9 are tables illustrating effects of voltage unbalance in the neutral point.

[0012]FIG. 10 is a space vector diagram illustrating vectors for use in an example home vertex computation.

DESCRIPTION

[0013]FIG. 1 is a circuit diagram of a conventional neutral point clamped (NPC) converter 10 including a three level output power conversion stage 12. The output power stage includes electrical switches 14 which may comprise, for example, IGBTs (Insulated Gate Bipolar Transistors), GTOs (Gate Turn Off Thyristors), or IGCTs (Integrated Gate Commutated Thyristors). The switches are paired with diodes 16, which may comprise anti-parallel freewheeling diodes, for example, to accommodate inductive motor load currents. A controller 24 is used for controlling each of the switches. The controller comprises a computer and in a preferred embodiment includes a digital signal processor. Output power conversion stage 12 includes individual NPC three level phase legs 18. Each phase leg of the three phase inverter has four switch and diode pairs spanning the DC bus (with a DC bus positive rail 20 (p), a DC bus negative rail 21 (n), and a midpoint of the bus 29 (the neutral point)) and two clamping diodes 22.

[0014] As described in aforementioned Lyons et al., U.S. Pat. No. 5,910,892, there are three command states for the switches per phase. Depending on the switch commanded state per phase, and the instantaneous polarity of the load current in that phase, the load current path can be through switches, freewheeling diodes, or clamping diodes. DC link capacitors 26 and 28 of split series connected DC capacitor bank 27 are coupled in series across the DC bus at neutral point 29. By coupling the clamping diodes 22 between the capacitor bank midpoint and pairs of the switches, the maximum DC working voltage across any switch is kept from exceeding about one half of the DC bus voltage (Vdc/2), provided the capacitor bank midpoint voltage is maintained at Vdc/2.

[0015] Embodiments of the present invention can be used with software algorithms for sine triangle modulation (FIGS. 2-5) or space vector modulation (FIGS. 6-10). By applying algorithms of embodiments of the present invention, a certain amount (depending on the voltage rating of the converter) of ripple in the neutral point can be compensated so as to minimize distortion in an output voltage waveform. Thus larger than average capacitors 26 and 28 are not required, and, in some embodiments, smaller than average capacitors can be used.

[0016] FIGS. 2-3 are graphs illustrating implementation of a sine triangle three level modulation. Although saw tooth shaped waveforms are shown in the embodiments of FIGS. 2-3 and FIGS. 4-5, the present invention is not limited to such waveforms. An alternative waveform, for example, is a triangle waveform.

[0017] In the embodiment of FIGS. 2-3, the modulating signals (V_(a)(t), V_(b)(t), v_(c)(t)) for each phase are calculated as follows: v_(a)(t) = m ⋅ sin (ω ⋅ t) + m₀ ${v_{b}(t)} = {{m \cdot {\sin \left( {{\omega \cdot t} - \frac{2 \cdot \pi}{3}} \right)}} + m_{0}}$ ${v_{c}(t)} = {{m \cdot {\sin \left( {{\omega \cdot t} + \frac{2 \cdot \pi}{3}} \right)}} + m_{0}}$

[0018] wherein v_(a)(t), V_(b)(t), v_(c)( t )∈[0,2], m₀ represents the zero sequence component, ω represents frequency, t represents time, and m represents the modulation index (the ratio between the desired amplitude of the output phase voltages and the maximum possible amplitude of undistorted sinusoidal phase voltages that can be generated).

[0019] When the modulating signal of phase x (a, b, or c) is larger than one, the modulating signal v_(x)(t) is compared with the upper triangular waveform, the output signal is switched to the positive rail 20 (FIG. 1) for the time d_(p)·T, and to the neutral point 29 (FIG. 1) for the time d₀·T. The times can be calculated as follows:

<d _(p)(t)>=v _(x)(t)−1

<d ₀(t)>=2−v _(x)(t),

[0020] wherein where <x(t)> denotes the function averaged over the switching cycle T_(s,) ${\langle{x(t)}\rangle} = {\frac{1}{T_{s}} \cdot {\int_{t}^{t + T_{s}}{{x(\tau)} \cdot {{\tau}.}}}}$

[0021] When the modulating signal of phase x is less than one, the modulating signal v_(x)(t) is compared with the lower triangular waveform, the output signal is switched to the neutral point 29 (FIG. 1) for the time d₀·T and to the negative rail 21 (FIG. 1) for the time d_(n)·T. The duty cycle times can be calculated as follows:

<d ₀(t)>=v _(x)(t)

<d _(n)(t)>=1−v _(x)(t).

[0022] Under some circumstances, voltage balance in the capacitor bank cannot be maintained on a switching cycle level, and low frequency voltage ripple results in the neutral point. Because conventional modulation embodiments compute the duty cycles d_(p), d₀, d_(n), assuming the balanced DC capacitor bank 27 voltage, a distorted ac output waveform results in the presence of the voltage ripple.

[0023] FIGS. 4-5 are graphs illustrating an implementation of a sine triangle three level modulation in accordance with one embodiment of the present invention wherein the amplitudes of the upper and lower triangular carrier are adjusted according to the amount of voltage unbalance in the capacitors in a feed forward manner. In the embodiment of FIGS. 4-5, the amplitudes of the triangular carriers are adjusted according to the ratio of the split DC link voltages (V_(p) and V_(n)) such that: $\frac{K_{p}}{K_{n}} = \frac{\left| V_{p} \right|}{\left| V_{n} \right|}$

[0024] wherein K_(p)+K_(n)=X and |V_(p)|+|V_(n)|=V_(pn)=V_(dc), and wherein X represents a constant which in one example has a value of 2.

[0025] The zero sequence component, m₀ still regulates the voltage balance in the capacitors. The duty cycles can be expressed as ${{\langle{d_{p}(t)}\rangle} = {{\frac{{v_{x}(t)} - K_{n}}{K_{p}}\quad {and}\quad {\langle{d_{o}(t)}\rangle}} = {{\frac{2 - {v_{x}(t)}}{K_{p}}\quad {for}\quad {v_{x}(t)}} > K_{n}}}},{and}$ ${{\langle{d_{o}(t)}\rangle} = \frac{v_{x}(t)}{K_{n}}}\quad,{{{and}\quad {\langle{d_{n}(t)}\rangle}} = {{\frac{K_{n} - {v_{x}(t)}}{K_{n}}\quad {for}\quad {v_{x}(t)}} < {K_{n}.}}}$

[0026] Therefore, the average ac voltage of the phase x, referenced to the neutral point can be expressed as: ${\langle{v_{0x}(t)}\rangle} = \left\{ \begin{matrix} {\left. {{\langle{d_{p}(t)}\rangle} \cdot} \middle| V_{p} \right| = {\left. {\frac{{v_{x}(t)} - K_{n}}{K_{p}} \cdot} \middle| V_{p} \right| = {{{\left( {{v_{x}(t)} - K_{n}} \right) \cdot \frac{V_{d\quad c}}{2}}\quad {for}\quad {v_{ref}(t)}} > K_{n}}}} \\ {\left. {{- {\langle{d_{n}(t)}\rangle}} \cdot} \middle| V_{n} \right| = {\left. {\frac{K_{n} - {v_{x}(t)}}{K_{n}} \cdot} \middle| V_{n} \right| = {{{\left( {{v_{x}(t)} - K_{n}} \right) \cdot \frac{V_{d\quad c}}{2}}\quad {for}\quad {v_{ref}(t)}} < K_{n}}}} \end{matrix} \right.$

[0027] such that there are no discontinuities when the modulating signal crosses the K_(n) boundary between upper and lower of the carrier waveform.

[0028] As discussed above, when the modulating signal of phase x (v_(0x)(t)) is larger than one, the modulating signal is compared with the upper triangular waveform, the output signal is switched to the positive rail 20 (FIG. 1) for the time d_(p)·T., and to the neutral point 29 for the time d₀·T, and, when the modulating signal is less than one, the modulating signal is compared with the lower triangular waveform, the output signal is switched to the neutral point for the time d₀·T and to the negative rail 21 for the time d_(n)·T.

[0029] The space vector diagrams of FIGS. 6-7 and the tables of FIGS. 8-9 illustrate effects of voltage unbalance in the neutral point on the small and medium voltage vectors. The large vectors are generally unaffected by the neutral point voltage.

[0030] Aforementioned Lyons et al., U.S. Pat. No. 5,910,892, describes an example of a conventional technique for space vector modulation wherein a controller uses the modulation to control a magnitude and a rotation of a reference voltage vector in a complex voltage plane defined by orthogonal axes and phase voltages. The feed-forward algorithm for space vector modulation of the present invention can be used to supplement the embodiment of this patent as well as other conventional space vector modulation embodiments.

[0031] A modified space vector three-level modulation algorithm of this embodiment of the present invention computes the duty cycles of the voltage switching vectors based on the actual location of the voltage vectors, as opposed to conventional algorithms that do not take into account the fact that switching vectors change their position if there is voltage unbalance in the neutral point. In circumstances when there is no neutral point unbalance, the modified algorithm computes the same duty cycles as the conventional space vector modulation algorithms.

[0032] The majority of conventional multilevel space vector modulation algorithms control the neutral point voltage balance by manipulating the redundant small vectors. Typically the controller determines the ratio of time that each small vector in a pair is switched during the duty cycle of any given small vector. Similarly, the controller in the space vector modulation algorithm explained in aforementioned Lyons et al., U.S. Pat. No. 5,910,892, determines the relative dwell times between two small vectors of the home vertex {right arrow over (V)}₀, {right arrow over (V)}₃ and assumes that {right arrow over (V)}₀={right arrow over (V)}₃.

[0033]FIG. 10 is a space vector diagram illustrating vectors for use in an example home vertex computation in accordance with an embodiment of the present invention. When the neutral point voltage is not exactly balanced, as shown in FIG. 10, the new home vertex {right arrow over (H)}_(v) can be computed from a neutral point controller command c and the actual location of the vectors

{right arrow over (H)} _(v) =c·{right arrow over (V)} ₀+(1−c)·{right arrow over (V)} ₃

[0034] where c∈[0,1] and represents a relative duty cycle compensation command selected to compensate for an imbalance between the voltages in DC capacitor bank 27 (FIG. 1). In one embodiment, for example, the difference between the DC link voltages V_(p) and V_(n) (that is, the error) is fed into a proportional integral regulator (not shown) which provides the compensation command.

[0035] Once the “new” home vertexes are calculated, the boundaries between triangular regions can be established and the nearest three vectors can be found. FIG. 10 illustrates an embodiment wherein the reference voltage vector {right arrow over (V)}* is located in an outer triangle region O. In that circumstance the duty cycles of the corresponding vectors are the ones that satisfy the equations

{right arrow over (V)}*=d _(H) ·{right arrow over (H)}+d _(M) ·{right arrow over (V)} _(M) +d _(L) ·{right arrow over (V)} _(L),

1=d _(H) +d _(M) +d _(L).

[0036] Wherein d_(H), d_(M), and d_(L) respectively represent the duty cycles of the home, medium, and large switching state vectors, and {right arrow over (H)}, {right arrow over (V)}_(M), and {right arrow over (V)}_(L) respectively represent the home, medium and large vectors. {right arrow over (V)}_(s) of FIG. 10 represents the small vector.

[0037] The small vectors duty cycles can then be found based on the duty cycle of the home vertex and the neutral point controller command as follows:

d ₀ =c·d _(H),

d ₃=(1−c))d _(H).

[0038] When the reference voltage vector {right arrow over (V)}* is located in one of the middle or inner triangle regions (M or I), the algorithm is similar except that that there different vectors to take into account in determining the boundary regions and in performing duty cycle computations.

[0039] After the duty cycles are calculated, whether by sine triangular or space vector techniques, controller 24 (FIG. 1) can use the duty cycles to determine gate timings for power electronic switches 14 and thus minimize effects of neutral point voltage ripple without requiring an increase in DC link capacitance. In one embodiment, the controller is an entirely software based system executed in a computer with interface circuits for voltage and current feedback data acquisition and digital timers for switch activations based on digital signal processor computed timings.

[0040] In some situations, the minimum pulse width constraint of the switches results in regions around the sector boundaries (represented by the dashed lines in FIG. 10) that can not be reached by reference voltage vector {right arrow over (V)}* and/or in increased error in small vector {right arrow over (V)}_(s).

[0041] In one embodiment of an error compensation technique, the controller is further adapted to calculate a voltage error caused by of a duty cycle time constraint at time n−1. More specifically, the voltage error ({right arrow over (e)}) can be defined as the difference between the reference voltage vector and the actual vector that was implemented ({right arrow over (V)}_(IMPL)) as follows:

{right arrow over (e)}(n−1)={right arrow over (V)}*(n−1)−{right arrow over (V)} _(IMPL)(N−1).

[0042] The error can then be compensated in the next switching cycle (at time n) if the controller is further adapted to modify a reference voltage vector by adding the voltage error to a command voltage vector ({right arrow over (V)}_(COM)) as follows:

{right arrow over (V)}*(n−1)={right arrow over (V)} _(COM)(n−1)+{right arrow over (e)}(n−1).

[0043] While only certain features of the invention have been illustrated and described herein, many modifications and changes will occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the invention. 

1. A high power motor drive converter comprising: a three level neutral point clamped (NPC) output power conversion stage including switches for supplying power to an AC drive motor; a split series connected DC capacitor bank coupled in parallel with the NPC output power conversion stage; and a controller for selecting switch positions for controlling the NPC output power conversion stage and compensating for a neutral point voltage imbalance of the DC capacitor bank by adjusting amplitudes of carrier voltages according to an amount of voltage imbalance in the split series connected DC capacitor bank.
 2. The converter of claim 1 wherein the controller is adapted for adjusting the amplitudes by using a ratio of DC voltages across the DC capacitor bank.
 3. The converter of claim 2 wherein the ratio is calculated as follows: $\frac{K_{p}}{K_{n}} = \frac{\left| V_{p} \right|}{\left| V_{n} \right|}$

wherein K_(p)+K_(n)=a constant, |V_(p)|+|V_(n)|=V_(dc), V_(dc) represents DC bus voltage, V_(p) represents positive rail DC bus voltage, and V_(n) represents negative rail DC bus voltage.
 4. The converter of claim 3 wherein the controller is adapted for adjusting the amplitudes by calculating modulating signals for each phase x as follows: v_(a)(t) = m ⋅ sin (ω ⋅ t) + m₀ ${v_{b}(t)} = {{m \cdot {\sin \left( {{\omega \cdot t} - \frac{2 \cdot \pi}{3}} \right)}} + m_{0}}$ ${v_{c}(t)} = {{m \cdot {\sin \left( {{\omega \cdot t} + \frac{2 \cdot \pi}{3}} \right)}} + m_{0}}$

wherein v_(a)(t), v_(b)(t), v_(c)(t)∈[0,2], m represents a modulation index, m₀represents the zero sequence component, ω represents frequency, and t represents time.
 5. The converter of claim 4 wherein the controller is adapted for adjusting the amplitudes by using the ratio and the modulating signals for each phase x to calculate switch position duty cycles as follows: ${{\langle{d_{p}(t)}\rangle} = {{\frac{{v_{x}(t)} - K_{n}}{K_{p}}\quad {and}\quad {\langle{d_{o}(t)}\rangle}} = {{\frac{2 - {v_{x}(t)}}{K_{p}}\quad {for}\quad {v_{x}(t)}} > K_{n}}}},{and}$ ${{\langle{d_{o}(t)}\rangle} = \frac{v_{x}(t)}{K_{n}}}\quad,{{{and}\quad {\langle{d_{n}(t)}\rangle}} = {{\frac{K_{n} - {v_{x}(t)}}{K_{n}}\quad {for}\quad {v_{x}(t)}} < {K_{n}.}}}$


6. The converter of claim 1 wherein the controller is adapted for adjusting the amplitudes by using space vector analysis to calculate switch position duty cycles based on actual locations of voltage vectors.
 7. The converter of claim 6 wherein the controller is adapted for calculating a new home vertex in response to a voltage unbalance in the DC capacitor bank.
 8. The converter of claim 7 wherein the controller is adapted for using the new home vertex to calculate a home vertex duty cycle and using the small vertex duty cycle to calculate the small vector duty cycles.
 9. The converter of claim 8 wherein the controller is further to calculate a voltage error caused by of a duty cycle time constraint at time n−1.
 10. The converter of claim 9 wherein the controller is further adapted to modify a reference voltage vector by adding the voltage error to a command voltage vector.
 11. A high power motor drive converter comprising: a three level neutral point clamped (NPC) output power conversion stage including switches for supplying power to an AC drive motor; a split series connected DC capacitor bank coupled in parallel with the NPC output power conversion stage; and a controller for selecting switch positions for controlling the NPC output power conversion stage and compensating for a neutral point voltage imbalance of the DC capacitor bank by using space vector analysis to calculate switch position duty cycles based on actual locations of voltage vectors to adjust amplitudes of carrier voltages according to an amount of voltage imbalance in the split series connected DC capacitor bank.
 12. The converter of claim 11 wherein the controller is adapted for calculating a new home vertex in response to a voltage unbalance in the DC capacitor bank.
 13. A method of controlling a high power motor drive converter including a three level neutral point clamped (NPC) output power conversion stage including switches for supplying power to an AC drive motor and a split series connected DC capacitor bank coupled in parallel with the NPC output power conversion stage, the method comprising: selecting switch positions for controlling the NPC output power conversion stage and compensating for a neutral point voltage imbalance of the DC capacitor bank by adjusting amplitudes of carrier voltages according to an amount of voltage imbalance in the split series connected DC capacitor bank.
 14. The method of claim 13 wherein adjusting the amplitudes comprises using a ratio of DC voltages across the DC capacitor bank.
 15. The method of claim 14 wherein the ratio is calculated as follows: $\frac{K_{p}}{K_{n}} = \frac{\left| V_{p} \right|}{\left| V_{n} \right|}$

wherein K_(p)+K_(n)=a constant, |V_(p)|+|V_(n)|=V_(dc), V_(dc) represents DC bus voltage, V_(p) represents positive rail DC bus voltage, and V_(n) represents negative rail DC bus voltage.
 16. The method of claim 15 wherein adjusting the amplitudes comprises calculating modulating signals for each phase x as follows: v_(a)(t) = m ⋅ sin (ω ⋅ t) + m₀ ${v_{b}(t)} = {{m \cdot {\sin \left( {{\omega \cdot t} - \frac{2 \cdot \pi}{3}} \right)}} + m_{0}}$ ${v_{c}(t)} = {{m \cdot {\sin \left( {{\omega \cdot t} + \frac{2 \cdot \pi}{3}} \right)}} + m_{0}}$

wherein v_(a)(t), V_(b)(t), V_(c)(t)∈[0,2], m represents a modulation index, m₀ represents the zero sequence component, ω represents frequency, and t represents time.
 17. The method of claim 16 wherein adjusting the amplitudes comprises using the ratio and the modulating signals for each phase x to calculate switch position duty cycles as follows: ${{\langle{d_{p}(t)}\rangle} = {{\frac{{\nu_{x}(t)} - K_{n}}{K_{p}}\quad {and}\quad {\langle{d_{0}(t)}\rangle}} = {{\frac{2 - {\nu_{x}(t)}}{K_{p}}\quad {for}\quad {\nu_{x}(t)}} > K_{n}}}},{and}$ ${{\langle{d_{0}(t)}\rangle} = \frac{\nu_{x}(t)}{K_{n}}},{{{and}\quad {\langle{d_{n}(t)}\rangle}} = {{\frac{K_{n} - {\nu_{x}(t)}}{K_{n}}\quad {for}\quad {\nu_{x}(t)}} < {K_{n}.}}}$


18. The method of claim 13 wherein adjusting the amplitudes comprises using space vector analysis to calculate switch position duty cycles based on actual locations of voltage vectors.
 19. The method of claim 18 wherein using space vector analysis comprises calculating a new home vertex in response to a voltage unbalance in the DC capacitor bank.
 20. The method of claim 19 wherein using space vector analysis further comprises using the new home vertex to calculate a home vertex duty cycle and using the small vertex duty cycle to calculate the small vector duty cycles.
 21. The method of claim 20 wherein adjusting the amplitudes further comprises calculating a voltage error caused by of a duty cycle time constraint at time n−1.
 22. The method of claim 21 wherein adjusting the amplitudes further comprises modifying a reference voltage vector by adding the voltage error to a command voltage vector. 